This application is based upon and claims priority from prior French Patent Application No. 02 06870, filed on Jun. 4, 2002, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The invention relates to integrated circuits, and especially but not exclusively to isolated-gate field-effect transistors (MOSFET transistors) of short gate length, for example less than 180 nanometers, and in particular those of nanoscale length, that is to say the gate length of which is less than about 100 nm.
2. Description of the Related Art
The fabrication of small-scale, particularly nanoscale, MOS transistors, of conventional architecture, is nowadays confronted with intrinsic problems that limit their operating characteristics.
Among such problems, the effects called xe2x80x9cshort channelxe2x80x9d effects (reduction in the threshold voltage of the transistor when the gate length decreases and consequently the channel length decreases) become predominant, thus therefore having a negative impact on the current characteristics of the transistors.
It is recognized that these xe2x80x9cshort channelxe2x80x9d effects are due to a reduction in the effective length of the conduction channel because of lateral diffusion (that is to say beneath the gate electrode) of the source and drain extension zones (usually called the xe2x80x9cLDD zonesxe2x80x9d by those skilled in the art).
One of the effective means of reducing these parasitic xe2x80x9cshort channelxe2x80x9d effects is to reduce the depth of the junctions of these extension zones, thereby reducing the lateral diffusion (which is proportional to the vertical depth of the junction) of these extension zones.
However, the reduction in depth of the junctions of these zones is accompanied by an increase in the layer resistance of these junctions when the depths become less than 40 nm in the case of the usual fabrication processes which provide an ion implantation of doping species (typically boron and arsenic) and then a heat activation by annealing at high temperature.
It should also be noted that depths of less than 30 nm are recommended in the case of CMOS technologies below 100 nm.
Furthermore, increasing the layer resistance of the junction increases the value of the parasitic resistance of the device, thus limiting the saturation current performance of the transistors.
Thus, technologists at the present time are confronted with the compromise between control of the short channel effects (that is to say control of the threshold voltage in order to keep the leakage current of the transistor below desired values) and the increase in the performance of the transistors (saturation current in the on state), this performance being partly governed by the value of the parasitic series resistance (and therefore the junction resistance).
One solution proposed consists in placing isolating lateral regions (spacers) on the sidewalls of the gate of the transistor, these being called offset spacers, allowing the lateral position of the LDD junctions to be offset during implantation of the latter. The use of deep (greater than 40 nm) junctions that are weakly resistive is then possible.
Such a solution makes it possible to control the effective conduction length of the channel via the width of the offset spacers, thus guaranteeing good control of the short channel effects while integrating low-resistivity junctions for enhanced current performance. However, integration of such a solution is confronted with technological production difficulties and the addition of expensive fabrication steps.
In particular, mention may be made, as technological difficulties, of the deposition of a conformal coating of a silicon-based material, the anisotropic and selective etching of this coating so as to stop on the active zone, whatever the surface density of the transistors, and the production of standard spacers that have to be readjusted.
This is because the offset spacers are usually made of silicon-based materials and it is consequently necessary to carry out anisotropic etching of the conformal coatings so as to reduce the thickness of the coatings at the base of the spacers, since, without this thickness reduction, the energy increase needed to pass through this stack in order to reach the active zone of the transistor (that is to say for producing the LDD zones) is such that the increase in the lateral dispersion of the dopants compensates for the offset provided by the offset spacers.
Furthermore, in some cases the lateral dispersion beneath the gate electrode is even degraded.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
Embodiments of the present invention aim to provide a solution to these problems.
In accordance with a broad aspect of the present invention a process produces a lateral offset of the junctions of the LDD zones in a very simple manner, without significantly modifying a standard fabrication process.
An embodiment of the present invention therefore provides a process for fabricating a MOS transistor, comprising a step of producing source and drain extension regions (LDD regions), consisting in forming a gate region on a semiconductor substrate and in implanting dopants into the substrate on either side of and at a certain distance from the gate of the transistor.
According to a general feature of the invention, the step of producing the source and drain extension regions consists in forming an intermediate layer on the sidewalls of the gate and on the surface of the substrate, this intermediate layer being formed from a material that is less dense than silicon dioxide. The implantation of dopants is then carried out through that part of the intermediate layer that is located on the surface of the substrate.
Thus, that part of the intermediate layer that is located on the vertical sidewalls of the gate allows the implantation to be offset laterally. Moreover, because of the low density of the material of the intermediate layer, the increase in implantation energy needed to pass through this layer remains low. Thus, compared with the conventional case, there remains a significant gain in terms of the lateral dispersion of the LDD junctions beneath the gate.
The invention therefore makes it possible for deep junctions to be easily integrated (without additional etching compared with the conventional process) while preserving the electrical length of the conduction channel.
The material forming the intermediate layer may advantageously be an anti-reflective material used as anti-reflective sublayer during exposure of a photoresist. Such a material is, for example, known by those skilled in the art by the name xe2x80x9cBARCxe2x80x9d (bottom anti-reflective coating) material available, for example, from Shipley. This material is an inorganic material used in photolithography to avoid parasitic reflections from the substrate during exposure of the resist.
The invention is therefore noteworthy in that it uses a material whose purpose and function were hitherto completely different from those intended here. Thus, whereas in the conventional photolithography process the anti-reflective coating is conventionally etched after the resist features have been developed, this layer of BARC-type material, deposited conformally and having a thickness varying between 1 and 100 nm, is, according to the invention, intentionally preserved after development of the resist features.
As a variant, it would also be possible to use, as intermediate layer material, porous silicon dioxide.
According to one method of implementing the invention, the material forming the intermediate layer (Cl) may be etched selectively with respect to silicon and the intermediate layer can be removed after the implantation of dopants. This is especially the case when the layer used is of the BARC type.
This being the case, as a variant, in particular when the material used for the intermediate layer is porous silicon, it is possible to leave a portion of the intermediate layer on the sidewalls of the gate and on part of the substrate after the implantation. Isolating lateral regions (spacers) resting on the sidewalls of the gate and on part of the substrate are therefore produced, these isolating lateral regions comprising the residual portion of the intermediate layer surmounted by another material, for example silicon nitride. The spacers finally produced are therefore bilayers.
Advantageously, the implantation energy is chosen so as to obtain a maximum dopant distribution at a depth of at least 3 to 4 nm.
The fact of being allowed to use, within the context of this invention, higher implantation energies makes it possible to limit the impact of the parasitic re-oxidation associated with the operation of etching the intermediate layer formed from BARC material, since the distribution of the dopants is located further away from the re-oxidized surface. The consumption of dopants in the oxide therefore remains marginal.
It should be noted that it is also possible to make the dopants diffuse, via a thermal activation annealing step, before the intermediate layer is removed, so as to prevent any parasitic surface effect due to the etching or to any subsequent cleaning operation.
The subject of the invention is also an integrated circuit comprising at least one transistor obtained by the process as defined above.
According to one embodiment, the transistor includes isolating lateral regions resting on the sidewalls of the gate and on part of the substrate, these isolating lateral regions comprising an intermediate layer formed from a material that is less dense than silicon oxide, for example porous silicon dioxide, this intermediate layer being surmounted by another material.